Device selection schemes in multi chip package nand flash memory system

ABSTRACT

Systems and methods are provided for perform device selection in multi-chip package NAND flash memory systems. In some embodiments, the memory controller performs device selection by command. In other embodiments, the memory controller performs device selection by input address.

RELATED APPLICATION

This application claims the benefit of U.S. Provisional PatentApplication No. 61/583,408 filed Jan. 5, 2012, which is herebyincorporated by reference in its entirety.

TECHNICAL FIELD

The present invention relates generally to semiconductor devices, forexample, flash devices.

BACKGROUND

Recently, NAND flash devices have become very popular with respect totheir use in mobile applications and mobile storage applications such asflash cards, digital audio/video players, cell phones, USB flash drivesand solid state drives (SSDs) for hard disk drive (HDD) replacement.With an increase in the density requirement in the market, NAND flashprovides high density with low cost.

NAND flash memories are described in, for example,

Kenichi Imamiya, et al., “A 125-mm2 1-Gb NAND Flash Memory With10-MByte/s Program Speed,” IEEE J Solid-State Circuits, vol. 37, no. 11,pp. 1493-1500, November 2002;

June Lee et al., “A 90-nm CMOS 1.8-V 2-Gb NAND Flash Memory for MassStorage Applications,” IEEE J Solid-State Circuits, vol. 38, no. 11, pp.1934-1942, November 2003;

Ken Takeuchi, et al., “A 56 nm CMOS 99 mm2 8 Gb Multi-level NAND FlashMemory with 10 MB/s Program Throughput,” ISSCC Dig. Tech. Paper, pp.144-145, February 2006.

SUMMARY

According to one broad aspect, the invention provides a memory systemcomprising: a memory controller; a plurality of memory devices connectedto the controller via a common bus with a multi-drop connection; whereinthe memory controller performs device selection by command.

According to another broad aspect, the invention provides a memorysystem comprising: a memory controller; a plurality of memory devicesconnected to the controller via a common bus with a multi-dropconnection; wherein the memory controller performs device selection byinput address; each memory device comprising: a register containing adevice identifier; a device identifier comparator that compares selectedbits of a received input address to contents of the register todetermine if there is a match, and wherein a given device is selected ifthe device identifier comparator of the given device determines there isa match.

According to another broad aspect, the invention provides a memorycontroller for use in a system comprising the memory controller and aplurality of memory devices connected to the controller via a common buswith a multi-drop connection, wherein the memory controller performsdevice selection by command.

According to another broad aspect, the invention provides a memorydevice for use in a system comprising a memory controller and aplurality of memory devices connected to the controller via a common buswith a multi-drop connection inclusive of the memory device, the memorydevice comprising: a command processor configured to process a commandreceived via the common bus to determine if the command selects thatparticular memory device, and to act upon the command if the commandselects that particular memory device.

According to another broad aspect, the invention provides a memorydevice for use in memory system comprising a memory controller, and aplurality of memory devices inclusive of the memory device connected tothe controller via a common bus with a multi-drop connection, the memorydevice comprising: a register containing a device identifier; a deviceidentifier comparator that compares selected bits of a received inputaddress to contents of the register to determine if there is a match,and wherein the memory device is selected if the device identifiercomparator determines there is a match.

According to another broad aspect, the invention provides a method in amemory system comprising a memory controller and a plurality of memorydevices connected to the controller via a common bus with a multi-dropconnection, the method comprising: performing device selection bycommand.

According to another broad aspect, the invention provides a method foruse in a memory system comprising a memory controller and a plurality ofmemory devices connected to the controller via a common bus with amulti-drop connection, the method comprising: the memory controllerperforming device selection by input address; each memory devicemaintaining a device identifier in a register; a device identifiercomparator in each memory device comparing selected bits of a receivedinput address to contents of the register of the memory device todetermine if there is a match, and wherein a given device is selected ifthe device identifier comparator of the given device determines there isa match.

Other aspects and features of the present invention will become apparentto those ordinarily skilled in the art upon review of the followingdescription of specific embodiments of the invention in conjunction withthe accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will now be described, by way ofexample only, with reference to the attached Figures, wherein:

FIG. 1 illustrates a NAND flash functional block;

FIG. 2 illustrates a NAND flash cell array structure;

FIG. 3 illustrates a NAND flash block structure;

FIG. 4 illustrates a NAND flash page structure;

FIG. 5 illustrates a page basis read operation in NAND flash;

FIG. 6 illustrates a page basis program operation in NAND flash;

FIG. 7 illustrates a block basis erase operation in NAND flash;

FIG. 8 illustrates a general system with flash memory;

FIG. 9 illustrates a flash memory system using a single flash memorydevice;

FIG. 10 illustrates a flash memory system using multiple flash memorydevices;

FIG. 11 illustrates NAND flash devices in multi-drop connection;

FIG. 12 illustrates NAND flash devices in multi-drop connection;

FIG. 13 illustrates a page program in two NAND flash devices;

FIG. 14 illustrates an interleave page program in two NAND flashdevices;

FIG. 15 illustrates a page read in two NAND flash devices;

FIG. 16 illustrates two NAND flash devices in a MCP according to oneembodiment of the present invention;

FIG. 17 illustrates four NAND flash devices in a MCP according toanother embodiment of the present invention;

FIG. 18 illustrates a command structure according to another embodimentof the present invention;

FIG. 19 illustrates an interleave page program in two NAND flash devicesaccording to another embodiment of the present invention;

FIG. 20 illustrates an interleave page read in two NAND flash devicesaccording to another embodiment of the present invention;

FIG. 21 illustrates an interleave page read and program in two NANDflash devices according to another embodiment of the present invention;

FIG. 22 illustrates example circuits for device selection by inputaddress;

FIG. 23 illustrates a command/address/data input timing; and

FIG. 24 illustrates command/address/data output timing.

DETAILED DESCRIPTION

The demand for memory capacity increase in flash memory systems hasbecome significant and a multi chip package (MCP: multiple chips in asingle package) is a very popular solution to increase packing density.However, the use of a separate chip enable pin (CE#) to each flashdevice in a single package requires system configuration changes (e.g.,pin assignment change, PCB change) when the number of flash devices in aMCP increases.

NAND Flash Functional Block

FIG. 1 illustrates a NAND flash functional block. Various inputs/outputsto the NAND functional block are depicted. In the following, # denotesactive low (i.e. enable when the signal input is Low).

Command Latch Enable (CLE) input signal 18 is used to control loading ofan operation mode command into an internal command register 38. Thecommand is latched into the command register 38 from the I/O port 28 onthe rising edge of the WE# signal 22 while CLE is High.

The Address Latch Enable (ALE) signal 20 is used to control loadingaddress information into the internal address register 40. Addressinformation is latched into the address register from the I/O port 28 onthe rising edge of the WE# signal 22 while ALE is High.

Chip Enable (CE#) 16: the device goes into a low-power Standby mode ifCE# goes High while the device is in Ready state. The CE# signal isignored while the device is in Busy state (R/B#=L), such as during aProgram or Erase or Read operation, and will not enter Standby mode evenif the CE# input goes High.

The Write Enable (WE#) signal 22 is used to control the acquisition ofdata from the I/O port 28.

The Read Enable signal (RE#) 24 controls serial data output. Data isavailable after the falling edge of RE#. The content of address registeris also incremented (Address=Address+I) on this falling edge.

I/O Port (I/O0 to 7) 28: I/O0 to I/07 pins are used as a port fortransferring address, command and input/output data to and from thedevice.

Write Protect (WP#) signal 26 is used to protect the device fromaccidental programming or erasing. The internal voltage regulator (highvoltage generator 32) is reset when WP# is Low. This signal is usuallyused for protecting the data during the power-on/off sequence when inputsignals are invalid.

Ready/Busy (R/B#) 14 is an open drain pin and the output signal is usedto indicate the operating condition of the device. The R/B# signal is inBusy state (R/B#=L) during the Program, Erase and Read operations andwill return to Ready state (R/B#=H) after completion of the operation.

Vcc 10 and Vss 12 are power supply inputs.

The memory core of NAND flash consists of NAND memory cell array 50, rowdecoder 52, sense amp & page buffer 54 and column decoder 56. Thedetailed memory cell array organization is described below. A page foreither read or program operation is selected by the row decoder 52. Ablock for erase operation is also selected by the row decoder. Duringread operation, the data of the selected page is sensed and latched intosense amp & page buffer 54. After that, the data stored in the pagebuffer 54 are sequentially read out through column decoder 56 and globalbuffers 44. During programming, the input data from global buffers 44are sequentially loaded into the page buffer 54 via column decoder 56.The input data latched in the page buffer are finally programmed intothe selected page.

High voltage generator 32 provides high voltages and reference voltagesduring read, program and erase operations.

Global buffers 44 temporarily hold and buffer input and output data viacommon I/O pins (I/O 0 to 7) 28. The common I/O pins serve as the portfor command, address and input/output data.

Status register 42 tracks the device status during read, program orerase operation.

Ready/Busy# 30 has an open drain transistor, and generates theReady/Busy (R/B#) signal 14 referenced above.

Command register 38 decodes an input command from the global buffer 44and the decoded command is input to the control circuit 36 having astate machine.

Control circuit 36 is a central unit to control the entire device duringvarious operating modes.

Control buffers 34 determine one of operating modes such as commandinput, address input, data input, data output and status output inaccordance with combination of control pins as CE#, CLE, ALE, WE#, RE#and WP#.

Multiplexed column address and row address are stored in the addressregister 40 and transferred into row pre decoder 46 and column decoder56 via column pre decoder 48.

An example of operational timing details and device operations for theNAND flash functional block of FIG. 1 can be found in NAND Flashspecifications such as Samsung's 8 Gb SLC NAND Flash Specificationk9f8g08×0 m entitled “1 G×8 Bit/2 G×8 Bit NAND Flash Memory” dated Mar.31, 2007 and Samsung's 16 Gb/32 Gb/64 Gb SLC NAND Flash Specification:k9xxg08uxm entitled “2 G×8 Bit/4 G×8 Bit/8 G×8 Bit NAND Flash Memory”dated Mar. 31, 2007, both of which are incorporated by reference herein.

Device Operation in NAND Flash

In this section, basic operations and cell array organization of NANDflash memory are described. FIG. 2 illustrates the cell array structureof NAND flash memory which consists of n erasable blocks labeled Block0, Block 1, . . . , Block n−1. Each block is subdivided into mprogrammable pages as shown FIG. 3, labeled Page 0, Page 1, . . . , Pagem−1.

Each page consists of (j+k) bytes (×8 b) as shown in FIG. 4. The pagesare further divided into a j-byte data storage region 100 (data field)with a separate k-byte area 102 (spare field). The k-byte area istypically used for error management functions. With this arrangement, 1page=(j+k) bytes, 1 block=m pages=(j+k) bytes * m, and the total memoryarray size=n blocks=(j+k) bytes * m * n.

In NAND flash devices, read and program operations are executed on apage basis while erase operations are executed on a block basis. Alloperations may, for example, be driven by commands specified in theabove-referenced Samsung specifications. In a specific example, j=4096,k=128, m=64 and n=2048. Using these numbers, 1 Page=(4K+128) Bytes, 1Block=64 Pages=(4K+128) Bytes×64=(256K+8K) Bytes, 1 Plane=2048Blocks=(256K+8K) Bytes×2048=(4 G+128M) Bits, and 1 Device=2 Planes=(4G+128M) Bits * 2=(8 G+256M) Bits. Typically, the stated memory capacityin NAND flash does not include the spare field.

The internal memory array is accessed on a page basis. The readoperation starts after writing READ command followed by addresses viacommon I/O pins (I/O0 to I/O 7) to the device. The 4,224 bytes of datawithin the selected page are sensed and transferred to the page register(or page buffer) in less than tR (data transfer time from flash array topage register) shown in FIG. 5. Once the 4,224 bytes of data are sensedand transferred from the selected page in the cell array to the dataregister, the data in the data register can be sequentially read fromthe device.

The memory array is programmed on a page basis. For program operations,a PROGRAM command followed by addresses and input data of 4,224 bytes isissued to the device through common I/O pins (I/O0 to 1/O7). The 4,224bytes of data are transferred to the page register (or page buffer)during input data loading cycles and finally programmed to the selectedpage of the cell array less than tPROG (page program time) as shown inFIG. 6.

The memory array is erased on a block basis. For block erase operations,a BLOCK ERASE command followed by block addresses is issued to thedevice through common I/O pins (I/O0 to 1/O7). The (256K+8K) bytes ofdata are erased less than tBERS (block erase time) as shown in FIG. 7.

General Flash Memory System

FIG. 8 shows a block diagram of an example of a general system thatincludes a flash memory system. The flash memory system 114 communicateswith a main system or processor 110 via a flash controller 112.

A typical flash memory system has either a single flash memory device118 as shown in FIG. 9 or multiple flash memory devices 120,122,124,126as shown in FIG. 10. A flash memory system using a single flash devicemight be used in applications which require relatively small memoryspace.

For applications requiring large memory space, a flash memory systemusing multiple flash memory devices can be implemented such as thesystem of FIG. 10. The flash controller 112 can access each flash memorydevice 120,122,124,126 via a common bus 128. Only one flash device canbe selected at a time by asserting a chip enable signal on one ofdevices.

NAND Flash Memory in Multi Chip Package (MCP)

A multi chip package (MCP: multiple chips in a single package) is a verypopular solution to increase packing density. An MCP typically usesmulti-drop bus such as shown in FIG. 11 and FIG. 12.

FIG. 11 illustrates a MCP having two NAND flash devices 130,132. Allinput and output signals except chip select (CE#) signals 136,138 ineach flash memory device are connected to a common bus 134. Each flashmemory device can be selected by asserting the appropriate CE# signal.For example, the flash device 1 130 can be selected and accessed byasserting CE1# 136 (CE1#=“Low”). The 2nd flash device 132 is unselected(CE2#=“High”) and ignores any input like commands or addresses from theflash controller. Also the output signals of the rest devices are highimpedance (i.e. Hi-Z) state.

Similarly FIG. 12 illustrates a MCP having four NAND flash devices140,142,144,146 with respective CE# signals CE1# 152, CE2# 154, CE3#156, and CE4# 158. The 1st flash device 1 140 can be selected andaccessed by asserting CE1# (CE1#=“Low”). The rest of the devices areunselected (CE2#=“High”, CE3#=“High”, CE4#=“High”) and ignore any inputlike commands or addresses from the flash controller. Also the outputsignals of the rest devices are high impedance (i.e. Hi-Z) state. Thistype of device connection is a multi-drop bus connection or topology.

FIG. 13 illustrates an example of page program operational timing fortwo NAND flash devices in a single package. All input and output pinsexcept CE# pins are commonly connected in multi-drop configuration asshown in FIG. 11. This example shows consecutive program operations intodevice 1 130 and device 2 132.

When CE1# is Low (400), the 1st command cycle (80 h) for page program isissued (402) to device 1 130. Five bytes input addresses (A0 to A30 for8 Gb NAND Flash) (404) and 4K bytes input data (406) are loaded todevice 1.

The 2nd command cycle (10 h) (408) for page program is asserted anddevice 1 starts page program operation (410) governed by auto-timed,internal program algorithm. During this period, the R/B# of device 1goes Low to represent device 1 is in busy state (412). Once the internalpage program operation is completed, the R/B# of device 1 goes High(414). Hence the next command can be issued to device 1. During pageprogram operation in device 1, device 2 132 is disabled (deselected) byCE2#=High (416).

When CE2# is Low (418), the 1st command cycle (80 h) for page program isissued to device 2 (420). Five bytes input addresses (AO to A30 for 8 GbNAND Flash) (422) and 4K bytes input data (424) are loaded to device 2.The 2nd command cycle (10 h) (426) for page program is asserted anddevice 1 starts page program operation governed by auto-timed, internalprogram algorithm. During this period, the R/B# of device 1 goes Low(428) to represent device 1 is in busy state. Once the internal pageprogram operation is completed, the R/B# of device 2 goes High (430).Hence the next command can be issued to device 2. During page programoperation in device 2, device 1 is disabled (deselected) by CE2#=High(432).

With page program operations shown in FIG. 13, the unselected NAND flashdevice waits until the selected device completes any operation. Theauto-timed page program typically takes 200 us in SLC NAND flash and 600us in MLC NAND flash.

In order to reduce the waiting time, a NAND flash device may have a “CE#don't care state.” Once the selected device starts an internal pageprogram operation, the selected device will continue the internal pageprogram operation even when the CE# is High. With the “CE# don't care”feature, the next device can perform any other operation once theprevious device enters the internal page program operation. This isreferred to as a device interleave operation between two NAND flashdevices and an example of this is shown in FIG. 14, again in the contextof the MCP of FIG. 11 containing 2 flash devices.

When CE1# is Low (440), the 1st command cycle (80 h) for page program isissued to device 1 130 (442). Five bytes input addresses (A0 to A30 for8 Gb NAND Flash) (444) and 4K bytes input data (446) are loaded todevice 1. The 2nd command cycle (10 h) (448) for page program isasserted and device 1 starts page program operation governed byauto-timed, internal program algorithm (450). During this period, theR/B# of device 1 goes ‘Low’ to represent device 1 is in busy state(452). Once the internal page program operation in the 1st devicestarted, which can be indicated by R/B#, the CE1# can return to High(454). Therefore the next page program command can be issued to the 2nddevice 132.

When CE2# is Low (456), the 1st command cycle (80h) for page program todevice 2 is issued (458). Five bytes input addresses (A0 to A30 for 8 GbNAND Flash) (460) and 4K bytes input data (462) are loaded to device 2.The 2nd command cycle (10 h) (464) for page program is asserted anddevice 2 starts page program operation governed by auto-timed, internalprogram algorithm (466). Once the internal page program operation iscompleted, the R/B# of device 2 goes High (468).

FIG. 15 shows interleave page read operational timing for two NAND flashdevices in a single package, for example, the MCP of FIG. 11. Theinterleave page read operation is very similar to the interleave pageprogram operation described previously. When CE1# is Low (470), the 1stcommand cycle (00 h) (472) for page read to device 1 130 is issued andfive bytes input addresses (A0 to A30 for 8 Gb NAND Flash) (474) areloaded to device 1.The 2nd command cycle (30 h) (476) for page read isasserted and device 1 starts page read operation governed by auto-timed,internal read algorithm. During this period, the R/B# of device 1 goesLow to represent device 1 is in busy state (480). Once the internal pageread operation is completed, the R/B# of device 1 goes High (482). Hencedevice 1 is ready for burst read operation of 4 KB data. During pageread operation for device 1, device 2 132 is disabled (deselected) byCE2#=High (484).

When CE2# is Low (486), the 1st command cycle (00 h) (488) for pageprogram to device 2 is issued and five bytes input addresses (A0 to A30for 8 Gb NAND Flash) (490) are loaded to device 2. The 2nd command cycle(10 h) (492) for page read is asserted and device 2 starts page readoperation governed by auto-timed, read algorithm (494). During thisperiod, the R/B# of device 2 goes Low to represent device 2 is in busystate (496). Once the internal page read operation is completed, theR/B# of device 2 goes High (498). Hence the next command can be issuedto device 2. During page read operation for device 2, device 1 isdisabled (deselected) by CE2#=High (500).

In MCP Configuration

An objective of MCP in flash memory is increasing memory capacity whilemaintaining same package pinout and configuration. However, inconventional implementations the chip enable (CE#) pin needs to beseparated as described in section 1.4. If the MCP device has 4 flashdevices in a single package, four chip enable pins (CE1#˜CE4#) areneeded as opposed to two in an MCP with two flash devices. The result isthat the 4-device MCP needs a different pin assignment and PCB layoutcompared to a 2-device MCP. In addition, this chip enable pin increaseis a burden to the flash memory controller.

The embodiments described below use only two flash devices in a singlepackage or flash memory system. However, these embodiments are easilyextended to be applicable to larger numbers of flash devices in a singlepackage or flash memory system.

Device Selection by Command in MCP

FIG. 16 and FIG. 17 show examples of device connection for two NANDflash devices in a single package and four NAND flash devices in asingle package. For the two device embodiment of FIG. 16, there are twoNAND flash devices 160,162 connected to a common bus 164. Unlike thearrangement of FIG. 11, there are no individual CE# pins. Similarly, forthe four device embodiment of FIG. 17, there are four NAND flash devices170,172,174,176 connected to a common bus 178. Unlike the arrangement ofFIG. 12, there are no individual CE# pins. In the illustrated examples,the pinout is identical regardless of the number of flash memory devicesin a package and all pins are commonly connected.

Some conventional NAND flash systems use a one byte command structure.No device ID is included in the command structure. FIG. 18 depicts a 1byte command structure according to an embodiment of the presentinvention. The command consists of OP code 200 and device ID 202. Inthis example, upper 4 bits (Bit 4 to Bit 7) are assigned to the OP codeand lower 4 bits (Bit 0 to Bit 3) are assigned to the device ID. With4-bit device ID, total 16 devices can be exclusively selected. Note thatthe number of bits assigned to OP code and device ID may vary and thecommand structure shown in FIG. 18 is just an example.

In some embodiments, each NAND flash device connected in a multi-dropconfiguration, for example the NAND flash devices of FIG. 16 or 17,contains a command processor (not shown) configured to process a commandreceived via the common bus to determine if the command selects thatparticular memory device, and to act upon the command if the commandselects that particular memory device.

Table 1 lists an example set of commands for use in an embodiment of thepresent invention. The lower 4 bits in the 1st command select one of upto 16 flash devices. A difference between the proposed NAND flashcommand and conventional NAND flash commands is that the lower 4 bits ofeach command in the example of the present invention are assigned to thedevice ID.

TABLE 1 Example Set of Commands Including Device ID Function 1st CommandCycle 2nd Command Cycle Read 0Xh 30h Burst Read (Additional 2Xh 30hCommand) Block Erase 6Xh D0h Read Status 7Xh — Page Program 8Xh 10h X =Device ID: 0~F up to 16 devices

Table 2 and Table 3 show read commands and page program commands havingdevice ID to select one of up to 16 flash devices.

TABLE 2 Read Command having Device ID Function 1st Command Cycle 2ndCommand Cycle Read Device 1 00h 30h Read Device 2 01h 30h Read Device 302h 30h . . . . . . . . . Read Device 16 0Fh 30h

TABLE 3 Page Program Command having Device ID Function 1st Command Cycle2nd Command Cycle Page Program Device 1 80h 10h Page Program Device 281h 10h Page Program Device 3 82h 10h . . . . . . . . . Page ProgramDevice 16 8Fh 10h

FIG. 19 illustrates operational timing of interleave page program in twoNAND flash devices according to an embodiment of the present invention.Note that the following interleave page operations can be also appliedto more than two flash devices in a system.

All flash devices (in this case, two flash devices) always accept anycommand. When CE# is Low (510), the 1st command cycle having device ID(80 h) (512) for page program is issued to device 1. Five bytes inputaddresses (A0 to A30 for 8 Gb NAND Flash) (514) and 4K bytes input data(516) are loaded to device 1, where:

1st address input (1st byte)=column address 1;

2nd address input (2nd byte)=column address 2;

3rd address input (3rd byte)=row address 1;

4th address input (4th byte)=row address 2;

5th address input (5th byte)=row address 3.

Device 2 will recognize from the 1st command cycle (80 h) that the inputaddress and input data are not for device 2. Thus device 2 will blockfollowing 5 bytes input address and 4K bytes input data from the commonbus (i.e. device 2 is deselected by the 1st command cycle (80 h)) (520).The 2nd command cycle (10 h) (518) for page program is asserted anddevice 1 starts page program operation governed by auto-timed, internalprogram algorithm (522). During this period, the R/B# of device 1 goesLow to represent device 1 is in busy state (524) Device 2 will ignorethe 2nd command cycle (10 h) because the 1st command cycle (80 h) wasnot for device 2. Once the internal page program operation in device 1started, which can be indicated by R/B#, the next page program commandcan be issued to device 2.

The 1st command cycle having device ID (81 h) (526) for page program todevice 2 is issued to device 2. Five bytes input addresses (A0 to A30for 8 Gb NAND Flash) (530) and 4K bytes input data (532) are loaded todevice 1. The internal page program operation in device 1 is notinterrupted by the 1st command cycle (81 h) for page program to device2. The 2nd command cycle (10 h) (534) for page program is asserted anddevice 2 starts page program operation governed by auto-timed, internalprogram algorithm (536). During this period, the R/B# of device 2 goesLow to represent device 2 is in busy state (538).

A read status command having device ID (70 h) is issued to check thestatus of device 1 (540). If device 1 is ready to take a next operation,another page program command can be inputted to device 1. The 1stcommand cycle having device ID (80 h) (542) for page program is issuedto device 1. Five bytes input addresses (A0 to A30 for 8 Gb NAND Flash)(544) and 4K bytes input data (546) are loaded to device 1. The 2ndcommand cycle (10 h) (548) for page program is issued and device 1starts page program operation governed by auto-timed, internal programalgorithm (550). During this period, the R/B# of device 1 goes Low torepresent device 1 is in busy state (552).

FIG. 20 illustrates operational timing of interleave page read in twoNAND flash devices according to an embodiment of the present invention.Note following interleave page operations can be also applied to morethan two flash devices in a system.

All flash devices (in this case, two flash devices) always accept anycommand. When CE# is ‘Low’ (560), the 1st command cycle (00 h) (562) forpage read to device 1 is asserted and five bytes input addresses (A0 toA30 for 8 Gb NAND Flash) (564) are loaded to device 1. Device 2 willrecognize from the 1st command cycle (00 h) that the input address arenot for device 2. Thus device 2 will block following 5 bytes inputaddress from the common bus (i.e. device 2 is deselected by the 1stcommand cycle (00 h)) (570). The 2nd command cycle (30 h) (566) for pageread is asserted and device 1 starts page read operation governed byauto-timed, internal read algorithm (568). During this period, the R/B#of device 1 goes Low to represent device 1 is in busy state (572).Device 2 will ignore the 2nd command cycle (30 h) because the 1stcommand cycle having device ID (00 h) is not for device 2.

The 1st command cycle (01 h) (580) for page read to device 2 is assertedand five bytes input addresses (A0 to A30 for 8 Gb NAND Flash) (582) areloaded to device 2. The 2nd command cycle (30 h) (584) for page read isasserted and device 2 starts page read operation governed by auto-timed,read algorithm (586). During this period, the R/B# of device 2 goes Lowto represent device 2 is in busy state (588).

A read status command having device ID (70 h) is issued to device 1 tocheck the device status (590). If device 1 is ready to take a nextoperation, another command can be inputted to device 1. The 1st commandcycle (20 h) (592) for burst read to device 1 is asserted and five bytesinput addresses (A0 to A30 for 8 Gb NAND Flash) (594) are loaded todevice 2. The 2nd command cycle (30 h) (596) for burst read is assertedand device 1 starts burst read operation to access 4K bytes data storedin the page buffers of device 1 during previous page read operation indevice 1 (598).

After burst reading the data from device 1, a read status command (71 h)is issued to check the status of device 2 (600). Device 1 will ignorethe read status command (71 h) because this command is not for thedevice 1. If device 2 is ready to take a next operation, another commandcan be inputted to device 2. The 1st command cycle (21 h) (602) forburst read to device 2 is asserted and five bytes input addresses (604)are loaded to device 2. The 2nd command cycle (30 h) (606) for burstread is asserted and device 2 starts burst read operation to access 4Kbytes data stored in the page buffers of device 2 during previous pageread operation in device 2 (608).

Similarly any device interleave operation among read, program and blockerase can be executed with an embodiment of the present invention. FIG.21 shows operational timing of interleave page read and program in twoNAND flash devices according to an embodiment of the present invention.

All flash devices (in this case, two flash devices) always accept anycommand. When CE# is Low (610), the 1st command cycle (00 h) (612) forpage read to device 1 is asserted and five bytes input addresses (A0 toA30 for 8 Gb NAND Flash) (614) are loaded to device 1. Device 2 willrecognize from the 1st command cycle (00 h) that the input address arenot for device 2. Thus device 2 will block following 5 bytes inputaddress from the common bus (i.e. device 2 is deselected by the 1stcommand cycle (00 h)) (620). The 2nd command cycle (30 h) (616) for pageread is asserted and device 1 starts page read operation governed byauto-timed, internal read algorithm (618). During this period, the R/B#of device 1 goes Low to represent device 1 is in busy state (622).Device 2 will ignore the 2nd command cycle (30 h) because the 1stcommand cycle (00 h) is not device 2.

The 1st command cycle having device ID (81 h) (624) for page program todevice 2 is issued to device 2. Five bytes input addresses (A0 to A30for 8 Gb NAND Flash) (628) and 4K bytes (630) input data are loaded todevice 1. The internal page program operation in device 1 is notinterrupted by the 1st command cycle (81 h) for page program to device2. The 2nd command cycle (10 h) (632) for page program is asserted anddevice 2 starts page program operation governed by auto-timed, internalprogram algorithm (634). During this period, the R/B# of device 2 goesLow to represent device 2 is in busy state (636).

A read status command (70 h) is issued to check the status of device 1(640). If device 1 is ready to take a next operation, another commandcan be inputted to device 1. The 1st command cycle (20 h) (642) forburst read to device 1 is asserted and five bytes input addresses (644)are loaded to device 1. The 2nd command cycle (30 h) (646) for burstread is asserted and device 1 starts burst read operation to access 4Kbytes data stored in the page buffers of device 1 during previous pageread operation in device 1 (648).

Device Selection by Input Address in MCP

In another embodiment, device selection is achieved through the use ofinput address, for example one or more MSB of the row address. Thecommand and sequence shown in Table 4 are identical to those ofconventional proposed NAND flash. It should be clearly understood adifferent command structure could be used.

TABLE 4 Example Command Set Function 1st Command Cycle 2nd Command CycleRead 00h 30h Burst Read (Additional 20h 30h Command) Block Erase 60h D0hRead Status 70h — Page Program 80h 10h Reset FFh —

In addition to the command, a full command cycle for read, burst read,block erase, page program includes an address. In the conventional 8 GBNAND flash design, the address contains 4 bytes, containing 32 bits A0to A31. Address bits A0 to A12 are assigned to the column address, andaddress bits A13 to A30 are assigned to the row address.

According to an embodiment of the invention, additional bits in of theaddress are used to select one of multiple devices that are commonlyconnected in a single package (e.g. MCP using multi-drop connection).

In a first example, for two 8 Gb flash devices, A31 can be used toperform device selection.

In a second example, for four 8 Gb flash devices, A31 and A32 can beused to perform device selection. Note this requires an additional bytein the address to convey A32. However, since the command and address areconveyed to the devices in sequence over the common bus, this does notchange the pinout requirement.

In a second example, for eight 8 Gb flash devices, A31 to A33 can beused to perform device selection. Note that this also requires anadditional byte in the address to convey A32 and A33. However, since thecommand and address are conveyed to the devices in sequence over thecommon bus, this does not change the pinout requirement.

Note that in addition to including address information for read, burstread, block erase, and page program, for this embodiment of theinvention, address information is also included for otherdevice-specific commands, such as read status.

To explain the device selection (e.g., input and output data control) byinput address, the case of 4 flash devices in MCP is described. FIG. 22shows one example of circuits for device selection by input address.Such a circuit is included in each NAND flash device connected in amulti-drop configuration. Refer to FIG. 1 for an example functionalblock diagram of a whole NAND flash. In FIG. 22, # denotes enable whenlogic Low (i.e. active when Low). CE#, WE#, RE#, WP#, ALE, CLE areexternal control input signals. CEf#, WEf#, REf#, WPf#, ALEf, CLEf arebuffered, internal control signals. I/O0˜I/O7 are external input andoutput signals (common I/O signals). I/Of0˜I/Of7 are buffered, internalinput and output signals. A31 and A32 are address signals from theaddress register. Device_ID register 300 is a register containing aunique device_ID—that is, unique between the devices connected in themulti-drop configuration. This can, for example, where the Device_IDregister of each device contains respective values for the bits ID_A32and ID_A31. be programmed by one of nonvolatile programming methods suchas laser fuse, electrical fuse, pad bonding option, metal layer optionor nonvolatile memory cells. An example of unique device ID informationstored in Device_ID register of the four devices of an MCP is shown inTable 5 below.

The device ID in each flash device in MCP is compared with input addressA31 and A32 whenever input addresses are loaded. Input address A31 andA32 via the global buffer are compared with device ID address ID_A31 andID_A32 in Device ID Comparator 302. If the input addresses are matchedwith the device ID addresses, the output IOEN 306 of the Device_IDComparator is High. WE# buffer and RE# buffer are controlled by not onlyCE# but also DSEL of the Burst Data Control block. Specifically, whenDSEL is high, these buffers are disabled.

A burst data control block 310 generates the DSEL outputs 320 as afunction of IOEN 306, ALEf 312 and CLEf 314. The burst data controlblock 310 receives IOEN 306, and inverts this with invertor 316 toproduce IOEN#. ALEf 312 is an input that is high during address input,and CLEf 314 is an input that is high during command input. ALEf 312,CLEf 314 and IOEN# are input to NOR gate 318 the output of which inputto inverter 319, the output of which is the DSEL output 320. DSEL lowmeans that a device is not de-selected, while DSEL high means a deviceis de-selected. It can be seen that during command input (CLEf=High) oraddress input (ALEf=High), the DSEL is always High. Therefore anycommand or address input to each device in MCP is not blocked by theBurst Data Control (i.e. DSEL=Low). In addition, the device that has adevice ID match is not de-selected.

Table 5 shows device selection table by input address for four flashdevices in MCP.

TABLE 5 Device Selection by Input Address Input Address (A32, A31) from5th Address Input Cycle ID_A32 ID_A31 0, 0 0, 1 1, 0 1, 1 Device 1 0 0Selected — — — Device 2 0 1 — Selected — — Device 3 1 0 — — Selected —Device 4 1 1 — — — Selected

FIG. 23 illustrates an example of command/address/data input timing withthe circuits shown in FIG. 22. Device 1 is selected and devices 2 to 4are deselected. For operational timing in FIG. 23, only devices 1 and 2are shown, but internal timing of devices 3 and 4 are identical to thatof device 2. Input address A32 (=0) and A31 (=0) at the 5th addresscycle are compared with device ID address ID_A31 and ID_A32 in theDevice ID Comparator. The IOEN in device 1 is High while the IOEN indevice 2 is Low. The DSEL in device 1 is Low (due to IOEN=High) anddoesn't disable the WE# buffer. Therefore following 4K byte input datafrom external pins are inputted to the Device 1 during data inputcycles. The DSEL in device 2 is High (due to IOEN=Low) and disables theWE# buffer. Therefore the buffered WEf# signal remains at ‘High’ andfollowing 4K byte input data to the Device 2 are not inputted to device1 during data input cycles. Devices 3 and 4 behave as device 2.

FIG. 24 illustrates command/address/data output timing with the circuitsshown in FIG. 22. The output timing is very similar to the input timingshown in FIG. 23. Device 1 is selected and devices 2 to 4 aredeselected. For operational timing in FIG. 23, only devices 1 and 2 areshown, but internal timing of devices 3 and 4 are identical to that ofdevice 2. Input address A32 (=0) and A31 (=0) at the 5th address cycleare compared with device ID address ID_A31 and ID_A32 in the Device IDComparator. The IOEN in device 1 is High while the IOEN in device 2 isLow. The DSEL in device 1 is Low (due to IOEN=High) and doesn't disablethe RE# buffer. Therefore 4K bytes read data can be accessed from device1 during burst data read cycles. The DSEL in device 2 is High (due toIOEN=Low) and disables the WE# buffer. Therefore the buffered REf#signal remains at High, which disables global buffers in device 2 andI/Of0 to I/Of7 remain at Hi-Z state. Devices 3 and 4 behave as device 2.

With the device selection method by input address described here, thedevice interleave operations (e.g., page program, interleave page readand interleave page read & program and so on) can be performed in samefashion as the device interleave operations described previously.

Operational timing and sequence for device interleave operations withthe device selection by input address are not shown because two examplesof device selection schemes (e.g., device selection by command anddevice selection by input address) are nearly identical.

In the embodiments described above, the device elements and circuits areconnected to each other as shown in the figures for the sake ofsimplicity. In practical applications these devices, elements circuits,etc., may be connected directly to each other or indirectly throughother devices elements, circuits, etc. Thus, in an actual configuration,the elements, circuits and devices are coupled either directly orindirectly with each other.

The above-described embodiments of the present invention are intended tobe examples only. Alterations, modifications and variations may beeffected to the particular embodiments by those of skill in the artwithout departing from the scope of the invention, which is definedsolely by the claims appended hereto.

1-9. (canceled)
 10. A memory system comprising: a memory controller; aplurality of memory devices connected to the controller via a common buswith a multi-drop connection; wherein the memory controller performsdevice selection by input address; each memory device comprising: aregister containing a device identifier; a device identifier comparatorthat compares selected bits of a received input address to contents ofthe register to determine if there is a match, and wherein a givendevice is selected if the device identifier comparator of the givendevice determines there is a match.
 11. The memory system of claim 10comprising: a global buffer in which command, data and input address areinitially stored upon receipt wherein the device identifier comparatorobtains the selected bits of the received input address via the globalbuffer.
 12. The memory system of claim 10 wherein each memory devicefurther comprises a burst data controller that causes the memory deviceto be selected: when the device identifier comparator determines thereis a match; while a command input is in progress; and while an addressinput is in progress.
 13. The memory system of claim 12 wherein in eachmemory device, the burst data controller comprises an output thatindicates whether the memory device is selected or deselected.
 14. Thememory system of claim 12 wherein each burst data controller comprises:a logic circuit that receives an output of the device identifiercomparator, an address latch enable signal that indicates whether anaddress input is in progress, and a command latch enable signal thatindicates whether a command input is in progress, and wherein the logiccircuit generates an output that indicates whether the memory device isselected or deselected.
 15. The memory system of claim 10 wherein eachmemory device further comprises: a write enable buffer for buffering areceived write enable signal, the write buffer having an input forreceiving an indication of whether that memory device is selected ordeselected, and wherein the write enable buffer is disabled when thememory device is deselected; a read enable buffer for buffering areceived read enable signal, the read buffer having an input forreceiving an indication of whether that memory device is selected ordeselected, and wherein the read enable buffer is disabled when thememory device is deselected.
 16. The memory system of claim 10 whereindevice selection is performed by input address with device interleaveoperations.
 17. The memory system of claim 16 wherein the interleaveoperation comprises one of: page program of a first device interleavedwith page program of a second device; page program of a first deviceinterleaved with page read of a second device; page read of a firstdevice interleaved with page read of a second device.
 18. The memorysystem of claim 10 wherein the plurality of devices comprises aplurality of NAND flash devices that are part of a multi-chip package.19. The memory system of claim 18 comprising: a common chip enable forthe plurality of NAND flash devices.
 20. The memory system of claim 10wherein the common bus comprises: a write protect line; a write enableline; a read enable line; an address latch enable line; a command latchenable line; a chip enable line; an I/O for command, address and data;and a ready/busy line. 21-38. (canceled)
 39. A memory device for use inmemory system comprising a memory controller, and a plurality of memorydevices inclusive of the memory device connected to the controller via acommon bus with a multi-drop connection, the memory device comprising: aregister containing a device identifier; a device identifier comparatorthat compares selected bits of a received input address to contents ofthe register to determine if there is a match, and wherein the memorydevice is selected if the device identifier comparator determines thereis a match.
 40. The memory device of claim 39 comprising: a globalbuffer in which command, data and input address are initially storedupon receipt wherein the device identifier comparator obtains theselected bits of the received input address via the global buffer. 41.The memory device of claim 39 further comprising: a burst datacontroller that causes the memory device to be selected: when the deviceidentifier comparator determines there is a match; while a command inputis in progress; and while an address input is in progress.
 42. Thememory device of claim 41 wherein the burst data controller comprises anoutput that indicates whether the memory device is selected ordeselected.
 43. The memory device of claim 41 wherein the burst datacontroller comprises: a logic circuit that receives an output of thedevice identifier comparator, an address latch enable signal thatindicates whether an address input is in progress, and a command latchenable signal that indicates whether a command input is in progress, andwherein the logic circuit generates an output that indicates whether thememory device is selected or deselected.
 44. The memory device of claim39 wherein the memory device further comprises: a write enable bufferfor buffering a received write enable signal, the write buffer having aninput for receiving an indication of whether that memory device isselected or deselected, and wherein the write enable buffer is disabledwhen the memory device is deselected; a read enable buffer for bufferinga received read enable signal, the read buffer having an input forreceiving an indication of whether that memory device is selected ordeselected, and wherein the read enable buffer is disabled when thememory device is deselected.
 45. The memory device of claim 39 whereindevice selection is performed by input address with device interleaveoperations.
 46. The memory device of claim 45 wherein the interleaveoperation comprises one of: page program of the memory deviceinterleaved with page program of a second device; page program of thememory device interleaved with page read of a second device; page readof the memory device interleaved with page read of a second device. 47.The memory device of claim 39 wherein the plurality of devices comprisesa plurality of NAND flash devices that are part of a multi-chip package.48. The memory device of claim 47 comprising: a common chip enable forthe plurality of NAND flash devices.
 49. The memory device of claim 39wherein the common bus comprises: a write protect line; a write enableline; a read enable line; an address latch enable line; a command latchenable line; a chip enable line; an I/O for command, address and data;and a ready/busy line. 50-58. (canceled)
 59. A method for use in amemory system comprising a memory controller and a plurality of memorydevices connected to the controller via a common bus with a multi-dropconnection, the method comprising: the memory controller performingdevice selection by input address; each memory device maintaining adevice identifier in a register; a device identifier comparator in eachmemory device comparing selected bits of a received input address tocontents of the register of the memory device to determine if there is amatch, and wherein a given device is selected if the device identifiercomparator of the given device determines there is a match.
 60. Themethod of claim 59 comprising: each memory device Initially storingcommand, data and input address are initially stored upon receipt in aglobal buffer wherein in each memory device the device identifiercomparator obtains the selected bits of the received input address viathe global buffer.
 61. The method of claim 59 further comprising: aburst data controller in each memory device causing the memory device tobe selected: when the device identifier comparator determines there is amatch; while a command input is in progress; and while an address inputis in progress.
 62. The method of claim 61 wherein in each memorydevice, the burst data controller generating an output that indicateswhether the memory device is selected or deselected.
 63. The method ofclaim 61 further comprising, in each memory device: in the burst datacontroller of the memory device: a) receiving in a logic circuit anoutput of the device identifier comparator of the memory device; b)generating an address latch enable signal that indicates whether anaddress input is in progress, c) generating a command latch enablesignal that indicates whether a command input is in progress, the methodfurther comprising the logic circuit generating an output that indicateswhether the memory device is selected or deselected.
 64. The method ofclaim 59 further comprising, in each memory device: buffering a receivedwrite enable signal in a write buffer, the write buffer having an inputfor receiving an indication of whether that memory device is selected ordeselected, and wherein the write enable buffer is disabled when thememory device is deselected; for buffering a received read enable signalin a read buffer, the read buffer having an input for receiving anindication of whether that memory device is selected or deselected, andwherein the read enable buffer is disabled when the memory device isdeselected.
 65. The method of claim 59 wherein device selection isperformed by input address with device interleave operations.
 66. Themethod of claim 65 wherein the interleave operation comprises one of:page program of a first device interleaved with page program of a seconddevice; page program of a first device interleaved with page read of asecond device; page read of a first device interleaved with page read ofa second device.
 67. The method of claim 59 wherein the plurality ofdevices comprises a plurality of NAND flash devices that are part of amulti-chip package.
 68. The method of claim 67 further comprising usinga common chip enable for the plurality of NAND flash devices.
 69. Themethod of claim 59 further comprising using a common bus comprising: awrite protect line; a write enable line; a read enable line; an addresslatch enable line; a command latch enable line; a chip enable line; anI/O for command, address and data; and a ready/busy line.